Pulse Testing for Battery Research
Measuring DC internal resistance, characterizing power capability, and simulating real-world load profiles — with precise pulse timing, flexible step configuration, and board-speed-aware procedure design.
Pulse Testing in Battery Research
From DCIR measurement and HPPC protocols to pulse step types and board timing constraints — a practical guide to designing and executing pulse test programs on automated battery test systems.
What Pulse Testing Is Used For
Pulse testing applies short-duration current excitations to a battery and measures the voltage response. The primary application is DC internal resistance (DCIR) measurement — a key indicator of power capability and aging state. Pulse testing is also used for Hybrid Pulse Power Characterization (HPPC), drive-cycle simulation, power fade analysis, and State of Health (SoH) estimation. Pulse precision is limited by the controller board speed and the power module's transient response.
Measuring DC Internal Resistance
DCIR is the most common pulse measurement and the simplest to implement:
- Rest the cell at a defined SoC until voltage is stable (typically 30–60 min rest).
- Apply a short current pulse — typically 1C or 2C, 10–30 seconds duration.
- Record the instantaneous voltage response at pulse start (ohmic component) and at pulse end (full polarization).
- DCIR = ΔV ÷ ΔI — compute from the voltage drop divided by the applied current.
- Follow with a rest step to allow voltage recovery before continuing the cycle.
- Repeat at multiple SoC points (e.g., 80%, 50%, 20%) for a complete resistance map.
Pulse Step Types and Timing
Maccor provides several step types and board settings for pulse work:
- Standard Discharge / Charge steps with Step Time End Type: Most straightforward for DCIR pulses — 1 ms minimum, 1 ms increments, 20 ms minimum period.
- Pulse Charge / Pulse Discharge step types: Dedicated high-speed pulse steps for repetitive pulsing sequences.
- GSM pulse mode (8-channel boards): 100 µs resolution, 4.6 ms fixed period. Requires GSM-capable board; set in Controller Board Configuration.
- Waveform step type: Apply arbitrary waveform-defined current profiles — useful for drive-cycle simulation and complex pulse patterns.
- External Pulse Charge step type: For specialized external pulse control hardware.
- C-Rate mode incompatibility: Never use C-Rate mode for pulse steps — use explicit current in Amps for precise timing.
Matching Board Speed to Pulse Requirements
Board speed directly limits what pulse timing is achievable:
- 50 ms boards: Minimum pulse duration ~50 ms. Suitable for long DCIR pulses (10–30 s) but not sub-100 ms work.
- 10 ms boards (8-channel): Minimum ~10 ms. Suitable for most DCIR applications; also supports GSM pulse mode (100 µs) for high-speed pulsing.
- 4.6 ms boards (4-channel): Minimum ~4.6 ms. Sub-5 ms pulse capability with 100 µs/5 ms pulse mode.
- 2 ms boards (1-channel): Minimum ~2 ms. Best available timing precision; 1.25 ms/1.25 ms pulse mode.
- Reporting during pulses: Set report frequency high enough to capture the full voltage transient — a step time report every 100 ms will miss the initial ohmic response on a 10-second pulse.
HPPC and Power Characterization Tests
The Hybrid Pulse Power Characterization (HPPC) test characterizes available power at each SoC point:
- Fully charge the cell with a standard CC-CV protocol.
- Rest for 1 hour at open circuit.
- Apply a 10-second discharge pulse at the target rate (typically 1C or defined by the standard).
- Rest for 40 seconds.
- Apply a 10-second charge pulse at a lower rate.
- Rest for 1 hour.
- Discharge 10% of rated capacity at C/25.
- Repeat the pulse sequence at the new SoC.
- Continue until the discharge cutoff voltage is reached.
Where Pulse Testing Adds Value
Pulse measurements provide information that DC cycling tests alone cannot supply.
| Application | Pulse Test Role |
|---|---|
| DCIR tracking over life | Embed 10-second pulse at each RPT to monitor resistance growth |
| Power fade analysis | HPPC at SOL and EOL quantifies available power loss |
| SoH estimation | Resistance vs. SoC maps support online SoH algorithms |
| EV drive-cycle simulation | Waveform step type applies real-world current profiles |
| Fast-charge optimization | Short charge pulses with recovery rests minimize plating risk |
Frequently Asked Questions
How long should a DCIR pulse be?
Standard DCIR pulses range from 2 to 30 seconds. A 2–5 second pulse captures primarily the ohmic resistance. A 10–30 second pulse includes kinetic polarization contributions as well. The duration should be standardized across all measurements in a study — mixing pulse durations produces non-comparable resistance values.
What report interval should I use during a DCIR pulse?
For a 10-second pulse, set a Step Time report at 0.1–0.5 s intervals. This captures the initial voltage drop (ohmic) at pulse start and the continued relaxation during the pulse. Too coarse a report interval misses the transient and produces a DCIR value that is actually a blend of ohmic and kinetic resistance.
Can I run HPPC and cycling in the same procedure?
Yes — insert the HPPC sequence as a sub-routine or as steps within the Do/Loop cycling structure at defined RPT intervals. For example, run 49 standard cycles, then run the full HPPC sequence on cycle 50, then repeat. This produces continuous cycling data with periodic HPPC snapshots without stopping and restarting the test.